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I am an Assistant Professor of Computer Science and Engineering at IIT Hyderabad. My key research interests are in the domain of computer architecture, embedded systems, and VLSI design automation.

I completed my Ph.D. from IIT Delhi and was advised by Prof. M. Balakrishnan and Prof. Kolin Paul. I was a recipient of Visvesvaraya Ph.D. fellowship supported by MeitY.

I completed my B.Tech. in ECE from MNIT Jaipur in 2006 and subsequently worked at Texas Instruments in Bangalore for 8+ years in various VLSI design activities - design for testability, verification, specification, and firmware development.



Teaching

Session Course Co-instructor
Jan 2022 - May 2022 Operating Systems - II Dr. Sathya Peri



Research

I am interested in research areas related to computer architecture, embedded systems, and VLSI design automation. The domain is quite broad and my current focus is in efficient thermal management of processors and memories, efficient management of shared resources in a system, and FPGA based accelerator design.

Open source releases

  1. CoMeT (Core and Memory Thermal Simulator): A first-ever integrated tool for thermal simulation of core and memory in a computing systemi, built over Sniper architecture simulator. Supports various integration of core and memory like 2D, 2.5D, and 3D. Many other useful features are also included. [Link to repository]

Technical Service

  1. Reviewer for leading conferences and journals like ASPDAC, DAC, IEEE ESL, CODES+ISSS, IEEE TCAD, ACM TECS

List of Publications

Recent list

  1. Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Joerg Henkel, and Preeti Ranjan Panda, "CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems", ACM Transactions on Architecture and Code Optimization (TACO). Accepted. [Preprint]

  2. Lokesh Siddhu, Rajesh Kedia, and Preeti Ranjan Panda. "CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance". In Design Automation and Test in Europe (DATE) 2022. Accepted.

  3. Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Joerg Henkel, Preeti Ranjan Panda, and Hussam Amrouch. "FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies". In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2022. [Link to paper]

Full list of publications is available here



Work Experience

Organization Period Summary of work
Khosla School of IT, IIT Delhi Jul 2020 - Dec 2021 Research work in thermal management of computer systems, modeling of caches, and shared resource management. I worked with Prof. Preeti Ranjan Panda during this period.
Texas Instruments India Pvt. Ltd. Jul 2006 - Dec 2014 Worked as a part of Microcontroller (MCU) design team: Design for Test (DfT), Functional Verification, Architecture Definition.



Others/ External Links

My dblp profile

My google scholar profile

My publons profile

My LinkedIn Page

My facebook page



Contact Details

Email: rkedia@cse.iith.ac.in

Office:
A-718/C, Academic block-A,
IIT Hyderabad,
Kandi, Sangareddy, Telangana - 502284.

Credits

Template borrowed from Styleshout




Image Gallery

defense
With Prof. Bala during online Ph.D. defense. A large number of attendees (in small circles on bottom) joined.
gian_iitg
With Prof. Sanjoy Baruah during GIAN course at IIT Guwahati in May 2018
profpeterIITD
With Prof. Peter Marwedel during his visit to IIT Delhi in 2018
vlsiddemo
Giving demo of MAVI at VLSID 2018
vlsidSahulasir
With Prof. Vineet Sahula at VLSID 2018, met him after many years
vlsidTut
At a tutorial on Assistive technologies by Prof. M. Balakrishnan at VLSID 2018
vlsid1
Attending VLSID 2017 in Hyderabad with Lokesh
vlsid2
Presenting MAVI paper in VLSID 2017
vlsid3
With Prof. Virendra Singh at VLSID 2017