Selected Research Publications (Author/co-Author):

  • Y. Pullaiah et al.,"Investigation of X-ray Irradiance Hardness and High Temperature Operation of H-Terminated Diamond MOSFET”, in IEEE Transactions on Electron Devices, Dec 2024. DOI: 10.1109/TED.2024.3514813. Online: https://ieeexplore.ieee.org/document/10805759.

  • K. Prashant and K. Nayak,"Contact Analysis of Elemental Transition Metal Electrodes for Complementary 2D-FET applications using MoS2 and WSe2”, in IEEE Electron Device Letters, vol.43, Issue 7, pp. 1137 - 1140, July 2022. DOI: 10.1109/LED.2022.3180083.

  • Y. Pullaiah et al.,"TCAD Analysis of O-terminated Diamond m-i-p+ Diode Characteristics Dependencies on Surface States CNL and Metal-Induced Gap States”, in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 271 - 277, January 2022. DOI: 10.1109/TED.2021.3129726.

  • S. Venkateswarlu et al.,"Electro-Thermal Performance Boosting in Stacked Si Gate-All-Around Nanosheet FET with Engineered Source/Drain Contacts”, in IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4723 - 4728, September 2021. DOI:10.1109/TED.2021.3095038.

  • A. Sudarsanan and K. Nayak,"TCAD Based Investigation of Statistical Variability Immunity in U-channel FDSOI n-MOSFET for sub-7nm Technology”, in IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2611 - 2617, June 2021. DOI: 10.1109/TED.2021.3074116.

  • A Sudarsanan and K. Nayak,"Immunity to random fluctuations induced by interface trap variability in Si gate-all-around n-nanowire field-effect transistor devices”, in Journal of Computational Electronics, Springer, April 2021. DOI: https://doi.org/10.1007/s10825-021-01692-w.

  • S. Venkateswarlu and K. Nayak,"Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around nano-sheet FET", in IEEE Transactions on Electron Devices, vol. 67, no. 10, October 2020. DOI: 10.1109/TED.2020.3017567.

  • S. Venkateswarlu and K. Nayak,"Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si CMOS Logic Circuit Performance in N-14 to N-7 scaled Technologies", in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1530-1536, April 2020. DOI:10.1109/TED.2020.2975416.

  • J. K. Tapar et al.,"Enhancing the optical gain in GaAs nanocylinders for nanophotonic applications," in AIP Journal of Applied Physics , vol. 127, no. 15, April 2020. DOI:10.1063/1.5132613.

  • A Sudarsanan et al.,"Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10 nm node SOI n-FinFET", in IEEE Transactions on Electron Devices , vol. 66, no. 11, November 2019. DOI:10.1109/TED.2019.2941896.

  • S. Venkateswarlu et al.,"Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si n-FinFET Performance", in IEEE Transactions on Electron Devices , vol. 65, no. 7, July 2018. DOI:10.1109/TED.2018.2834979.

  • M. Bajaj et al.,"Effect of metal gate granularity induced random fluctuations on Si gate-all-around nanowire MOSFET 6-T SRAM cell stability", in IEEE Transactions on Nanotechnology , vol. 15, no. 2, Mar. 2016. DOI:10.1109/TNANO.2016.2515638.

  • K. Nayak et al.,“Random dopant fluctuation induced variability in undoped channel Si gate-all-around nanowire n-MOSFET,” in IEEE Transactions on Electron Devices , vol. 62, no. 2, pp. 685-688, Feb. 2015. DOI:10.1109/TED.2014.2383352.

  • A. Konar et al.,“Carrier transport in high mobility InAs nanowire junctionless transistors,” in Nano Lett. 2015, 15, 3, 1684–1690. DOI:https://doi.org/10.1021/nl5043165.

  • K. Nayak et al.,"Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs," in IEEE Transactions on Electron Devices ,vol. 61, no. 11, pp. 3892-3895, Nov. 2014. DOI:10.1109/TED.2014.2351401.

  • K. Nayak et al.,"CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET", in IEEE Transactions on Electron Devices ,vol. 61, no. 9, pp. 3066-3074, Sept. 2014. DOI:10.1109/TED.2014.2335192.

  • K. Nayak et al.,"Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits", in Jpn. J. Appl. Phys,vol. 53, no. 4S, Feb. 2014. DOI:10.7567/JJAP.53.04EC16.

  • B. Bhushan et al.,“DC compact model for SOI tunnel field-effect transistors,” in IEEE Transactions on Electron Devices ,vol. 59, no. 10, pp. 2635 – 2642, Oct 2012. DOI:10.1109/TED.2012.2209180.

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