Kaushik Nayak
 Kaushik Nayak

 

Experience:

  • Associate Professor: Dept. of Electrical Engineering, IIT Hyderabad, India; (October 2021 - Current).


  • Assistant Professor: Dept. of Electrical Engineering, IIT Hyderabad, India; (August 2015 - October 2021).


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    Research Interests:

    Electron Devices Physics; Mesoscopic Electronics.

     

    Courses Taught:

    (Dept. of Electrical Engineering)

  • EE 6440 Extreme Environment Physical Electronics
  • EE 4110 Physics of Electrical Engineering Materials
  • EE 6180 Semiconductor Heterojunction Devices Physics
  • EE 5181 Semiconductor Devices Modeling
  • EE 6170 Mesoscopic Device Electronics
  • EE 6160 Mesoscopic Carrier Transport
  • EE 5117 Microelectronic Device Physics
  • EE 5107 Semiconductor Physical Electronics
  • EE 5110 Semiconductor Devices and Modeling
  • EE 6120 Nanoelectronics Principles and Devices
  • EE 5111 Microelectronics and Device Simulation Laboratory
  • EE 5159 Microfabrication and Device Simulation Laboratory
  • EE 3010 Electromagnetic Waves and Transmission Lines
  • EE 2330 Antenna Design
  • EE 3302 Electromagnetic Wave Propagation

     

    (Dept. of Climate Change)

  • CC 5010 Earth's Evolution and Paleoclimate
  • CC 5110 Earth's Climate and Atmospheric Sciences
  • CC 5130 Atmospheric Electricity


    • Professional Society:

  • Senior Member: IEEE; IEEE Electron Devices Society; IEEE Antennas & Propagation Society.


  • Regular Member: American Physical Society.


    Selected Research Publications:

  • Kumar Prashant, and Kaushik Nayak, "Contact Analysis of Elemental Transition Metal Electrodes for Complementary 2D-FET applications using MoS2 and WSe2”, in IEEE Electron Device Letters, vol.43, Issue 7, pp. 1137 - 1140, July 2022. DOI: 10.1109/LED.2022.3180083.

  • Yerragudi Pullaiah, Mohit Bajaj, Oves Badami, and Kaushik Nayak, "TCAD Analysis of O-terminated Diamond m-i-p+ Diode Characteristics Dependencies on Surface States CNL and Metal-Induced Gap States”, in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 271 - 277, January 2022. DOI: 10.1109/TED.2021.3129726.

  • Sankatali Venkateswarlu, Oves Badami, and Kaushik Nayak, "Electro-Thermal Performance Boosting in Stacked Si Gate-All-Around Nanosheet FET with Engineered Source/Drain Contacts”, in IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4723 - 4728, September 2021. DOI:10.1109/TED.2021.3095038.

  • Akhil Sudarsanan, and Kaushik Nayak, "TCAD Based Investigation of Statistical Variability Immunity in U-channel FDSOI n-MOSFET for sub-7nm Technology”, in IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2611 - 2617, June 2021. DOI: 10.1109/TED.2021.3074116.

  • Akhil Sudarsanan, and Kaushik Nayak, "Immunity to random fluctuations induced by interface trap variability in Si gate-all-around n-nanowire field-effect transistor devices”, in Journal of Computational Electronics, Springer, April 2021. DOI: https://doi.org/10.1007/s10825-021-01692-w.

  • Sankatali Venkateswarlu, and Kaushik Nayak, "Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around nano-sheet FET", in IEEE Transactions on Electron Devices, vol. 67, no. 10, October 2020. DOI: 10.1109/TED.2020.3017567.

  • Sankatali Venkateswarlu, and Kaushik Nayak, "Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si CMOS Logic Circuit Performance in N-14 to N-7 scaled Technologies", in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1530-1536, April 2020. DOI:10.1109/TED.2020.2975416.

  • Jinal Tapar, Saurabh Kisen, Kumar Prashant, Kaushik Nayak, and Naresh Kumar Emani, "Enhancing the optical gain in GaAs nanocylinders for nanophotonic applications," in AIP Journal of Applied Physics , vol. 127, no. 15, April 2020. DOI:10.1063/1.5132613.

  • Akhil Sudarsanan, Sankatali Venkateswarlu, and Kaushik Nayak, "Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10 nm node SOI n-FinFET", in IEEE Transactions on Electron Devices , vol. 66, no. 11, November 2019. DOI:10.1109/TED.2019.2941896.

  • Sankatali Venkateswarlu, Akhil Sudarsanan, Shiv Govind Singh, and Kaushik Nayak, "Ambient Temperature Induced Device Self-heating Effects on Multi-Fin Si n-FinFET Performance", in IEEE Transactions on Electron Devices , vol. 65, no. 7, July 2018. DOI:10.1109/TED.2018.2834979.

  • Mohit Bajaj, Kaushik Nayak, Suresh Gundapaneni and V. Ramgopal Rao, "Effect of metal gate granularity induced random fluctuations on Si gate-all-around nanowire MOSFET 6-T SRAM cell stability", in IEEE Transactions on Nanotechnology , vol. 15, no. 2, Mar. 2016. DOI:10.1109/TNANO.2016.2515638.

  • Kaushik Nayak, Samarth Agarwal, Mohit Bajaj, K. V. R. M. Murali, and V. Ramgopal Rao, “Random dopant fluctuation induced variability in undoped channel Si gate-all-around nanowire n-MOSFET,” in IEEE Transactions on Electron Devices , vol. 62, no. 2, pp. 685-688, Feb. 2015. DOI:10.1109/TED.2014.2383352.

  • A. Konar, J. Mathew, K. Nayak, M. Bajaj, R. K. Pandey, S. Dhara, K. V. R. M. Murali, and Mandar Deshmukh, “Carrier transport in high mobility InAs nanowire junctionless transistors,” in Nano Lett. 2015, 15, 3, 1684–1690. DOI:https://doi.org/10.1021/nl5043165.

  • K. Nayak, S. Agarwal, M. Bajaj, P. J. Oldiges, K. V. R. M. Murali and V. R. Rao, "Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs," in IEEE Transactions on Electron Devices ,vol. 61, no. 11, pp. 3892-3895, Nov. 2014. DOI:10.1109/TED.2014.2351401.

  • Kaushik Nayak, Mohit Bajaj, Aniruddha Konar, Philip J. Oldiges, Kenji Natori, Hiroshi Iwai, K. V. R. M. Murali, and V. Ramgopal Rao, "CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET", in IEEE Transactions on Electron Devices ,vol. 61, no. 9, pp. 3066-3074, Sept. 2014. DOI:10.1109/TED.2014.2335192.

  • Kaushik Nayak, Mohit Bajaj, Aniruddha Konar, Philip J. Oldiges, Hiroshi Iwai, K. V. R. M. Murali, and V. Ramgopal Rao, "Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits", in Jpn. J. Appl. Phys,vol. 53, no. 4S, Feb. 2014. DOI:10.7567/JJAP.53.04EC16.

  • Bharat Bhusan, Kaushik Nayak, and V. Ramgopal Rao, “DC compact model for SOI tunnel field-effect transistors,” in IEEE Transactions on Electron Devices ,vol. 59, no. 10, pp. 2635 – 2642, Oct 2012. DOI:10.1109/TED.2012.2209180.span>

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